As a result of the rapid technological growth of the past several decades, transistors and other semiconductor devices have become a fundamental building block for a wide range of electronic devices. As the performance demands on these electronic devices increases, there is a need for electronic circuits that are smaller and faster. With transistor performance approaching theoretical limits, minimizing the performance effect caused by interconnect between logic gates becomes an increasingly important aspect of device design.
In many respects, however, the evolution of electronic design automation (EDA) tools has not kept pace with the increases in performance demands. As a result, there is a need for EDA tools and design techniques that provide flexibility in optimizing the properties of electronic circuits to maximize overall device performance In particular, the ability to optimize the location, spacing, and/or dimensions of interconnect within electronic devices has become critical to maximizing performance.
Additionally, as electronic devices have evolved to meet ever-increasing performance demands, many of the assumptions, parameters, and constraints utilized by conventional EDA tools are not applicable to or optimal for designing such devices. For example, recent development efforts have produced semiconductor devices, such as improved junction field effect transistors (JFETs), that provide improved performance under certain circumstances in comparison to the conventional metal-oxide semiconductor field-effect transistors (MOSFETs) that are commonly used in electronic devices. There is thus a need for design methodologies and EDA tools capable of optimizing the design of circuits that incorporate such semiconductor devices.